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Cited by 326

The DOI matches its Crossref record; 20 of the 20 references it cites were found in a registry or an index.

Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements

Lelis, Aivars J., Habersat, Daniel, Green, Ronald, Ogunniyi, Aderinto, Gurfinkel, Moshe, Suehle, John, Goldsman, Neil·2008·IEEE Transactions on Electron Devices

Abstract

We have observed significant instability in the threshold voltage of 4H-SiC metal-oxide-semiconductor field-effect transistors due to gate-bias stressing. This effect has a strong measurement time dependence. For example, a 20-mus-long gate ramp used to measure the I-V characteristic and extract a threshold voltage was found to result in a instability three to four times greater than that measured with a 1-s-long gate ramp. The VTinstability was three times greater in devices that did not receive a NO postoxidation anneal compared with those that did. This instability effect is consistent with electrons directly tunneling in and out of near-interfacial oxide traps, which in irradiated Si MOS was attributed to border traps.

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Metadata

Authors
Lelis, A. J., Habersat, D., Green, R., Ogunniyi, A., Gurfinkel, M., Suehle, J., & Goldsman, N.
Venue
IEEE Transactions on Electron Devices
Published
2008-08
Volume
55
Issue
8
Pages
1835-1840
ISSN
0018-9383 (ISSN-L)
OpenAlex
W2121387826
Cited by
326
References
20
FWCI
7.47
Type
journal article
Language
en
Open access
closed

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Lelis, A. J., Habersat, D., Green, R., Ogunniyi, A., Gurfinkel, M., Suehle, J., & Goldsman, N. (2008). Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements. IEEE Transactions on Electron Devices. https://doi.org/10.1109/ted.2008.926672

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