Cited by 73Silicon Carbide Semiconductor TechnologiesElectronic Packaging and Soldering Technologies3D IC and TSV technologies

Review of Topside Interconnections for Wide Bandgap Power Semiconductor Packaging

Open access
Wang, Lisheng, Wang, Wenbo, Hueting, Raymond J. E., Rietveld, Gert, Ferreira, Jan Abraham·2023·IEEE Transactions on Power Electronics

Abstract

Due to their superior material properties, wide bandgap (WBG) semiconductors enable the application of power electronics at higher temperature operation, higher frequencies, and higher efficiencies compared to silicon (Si). However, the commonly-used aluminum wire bonding as topside interconnection technology prevents WBG semiconductors from reaching their full potential, due to inherent parasitic inductances, large size, heat dissipation, and reliability issues of wire bonding technology. Therefore, this article presents a comprehensive review of topside interconnection technologies of WBG semiconductor power devices and modules. First, the challenges and driving factors for the interconnection of WBG semiconductor dies are discussed. Second, for each widely commercially used WBG semiconductor, i.e., silicon carbide and gallium nitride, technical details and innovative features of state-of-the-art interconnection techniques in packages are reviewed. Then, the majority of existing topside interconnection materials for WBG semiconductors are categorized and compared, followed by a discussion of their advantages, challenges, and failure modes. Based on this elaborate discussion, potential future directions of the interconnection technology development are given. It is concluded that the superior performance of WBG semiconductors can be obtained by combining novel materials with innovative designs for the topside interconnections.

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Crossref · 10.1109/tpel.2022.3200469

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  • Embedded packaging with substrate-embedded microchannels enables more than 22% higher saturation current due to improved thermal uniformity.

    “When combined with substrate-embedded microchannels for localized convective cooling, the junction temperature can drop by approximately 50 ◦ C, enabling more than 22% [27] higher saturation current due to improved thermal uniformity.”

    From Thermal Management of Wide-Bandgap Power Semiconductors: Strategies and Challenges in SiC and GaN Power Devices (2025) · cites this paper as [27]

    The Embedded Packaging Technology section (page unavailable) says embedded packaging can enhance thermal performance and permit double-sided cooling. It does not report substrate-embedded microchannels, an approximately 50 °C junction-temperature drop, or a greater-than-22% increase in saturation current due to improved thermal uniformity. (LLM, conf=0.78)

    Experimental — accuracy not yet measured
  • Double-sided cooling achieves thermal resistance reduction of 20-48% versus single-sided cooling.

    “• R th reduction: 20-48% (vs. single-sided) [27,42]”

    From Thermal Management of Wide-Bandgap Power Semiconductors: Strategies and Challenges in SiC and GaN Power Devices (2025) · cites this paper as [27]

    The “D. 3-D Interconnection Technology” section reports that Cu-clip double-sided cooling reduces junction-to-case thermal resistance by about 20% versus single-sided cooling in a wire-bonded package. It does not support the claimed 48% upper bound, so the full 20–48% range is not established by this source. (LLM, conf=0.88)

    Experimental — accuracy not yet measured
  • Realizing device-level advantages at the system level requires a multidisciplinary co-design approach that jointly considers device physics, packaging, circuit topologies, gate drivers, EMI filters, and cooling beyond optimizing isolated components.

    “Realizing these device-level advantages at the system level, however, requires a multidisciplinary co-design approach that jointly considers device physics, packaging, circuit topologies, gate drivers, EMI filters, and cooling-beyond optimizing isolated components [10-12,27,80,81].”

    From Thermal Management of Wide-Bandgap Power Semiconductors: Strategies and Challenges in SiC and GaN Power Devices (2025) · cites this paper as [27]

    The discussion of future trends (page unavailable) calls for whole-system integration to improve power density and efficiency in high-frequency applications. The parasitic-inductance section (page unavailable) also discusses circuit design, gate drivers, and EMI filters. But the paper does not explicitly call for the claimed joint co-design of every listed element, including device physics and cooling, rather than optimization of isolated components. (LLM, conf=0.85)

    Experimental — accuracy not yet measured
  • Cu-based interconnections such as Cu clips and Cu sintering can cut loop inductance from 14 nH to 2.37 nH versus wire bonding, thereby lowering EMI and switching losses.

    “Cu-based interconnections (Cu clips, Cu sintering, etc.) can cut loop inductance from 14 nH to 2.37 nH versus wire bonding, thereby lowering EMI and switching losses [25,27].”

    From Thermal Management of Wide-Bandgap Power Semiconductors: Strategies and Challenges in SiC and GaN Power Devices (2025) · cites this paper as [27]

    In “D. 3-D Interconnection Technology” (page unavailable), the review says a Cu-clip package reduces inductance by 50% relative to wire bonding; it also reports lower switching loss for a different Cu-pin structure. It does not substantiate the claimed reduction from 14 nH to 2.37 nH, or attribute that reduction and lower EMI to Cu clips and Cu sintering. (LLM, conf=0.88)

    Experimental — accuracy not yet measured
  • Copper-clip structures reduce thermal resistance by approximately 20% versus single-sided layouts.

    “Copperclip structures reduce thermal resistance by approximately 20% [27] versus single-sided layouts, while flip-chip bonding further mitigates parasitic inductance.”

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Cites

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4 of the 115 references couldn’t be matched to a known paper.

Research works printed but not linked: 12

  1. [10]10. M. Hutter, C. Weber, C. Ehrhardt, and K. Lang, "Comparison of different technologies for the die attach of power semiconductor devices conduct- ing active power cycling," in Proc. 9th Int. Conf. Integr. Power Electron. Syst., 2016, pp. 1-7.
  2. [11]11. S. Duch, T. Krebs, and W. Schmitt, "Comparison of thermal measurement methods and determination of thermal resistance of die attach materials used in power electronic modules," in Proc. 9th Int. Conf. Integr. Power Electron. Syst., 2016, pp. 1-6.
  3. [46]46. K. Guth et al., "New assembly and interconnects beyond sintering meth- ods," in Proc. Int. Exhib. Conf. Power Electron., Intell. Motion, Renew. Energy, Energy Manage., 2010, pp. 232-237.
  4. [55]55. M. Becker et al., "FEM based enhancement of system lifetime by im- provement of the die top connection of power electronic semiconductors," in Proc. 10th Int. Conf. Integr. Power Electron. Syst., 2018, pp. 1-4.
  5. [59]59. S. Behrendt et al., "Feasibility of copper-based ribbon bonding as an assembly method for advanced power modules," in Proc. Int. Exhib. Conf. Power Electron., Intell. Motion, Renew. Energy, Energy Manage., 2018, pp. 1-8.
  6. [63]63. S. Eicher et al., "4.5 kV press pack IGBT designed for ruggedness and reliability," in Proc. IEEE 39th IAS Annu. Meeting Ind. Appl. Conf., 2004, pp. 1534-1539.
  7. [71]71. T. Ueda, N. Yoshimatsu, N. Kimoto, D. Nakajima, M. Kikuchi, and T. Shinohara, "Simple, compact, robust and high-performance power module T-PM (transfer-molded power module)," in Proc. 22nd Int. Symp. Power Semicond. Devices IC's, 2010, pp. 47-50.
  8. [72]72. T. Nishimura, K. Mimura, K. Yamamoto, S. Idaka, and T. Shinohara, "High heat dissipation and high heat durability technologies for transfer- molded power modules with insulating sheets," in Proc. 9th Int. Conf. Integr. Power Electron. Syst., 2016, pp. 1-5.
  9. [77]77. P. Beckedahl, S. Buetow, A. Maul, M. Roeblitz, and M. Spang, "400 A, 1200 V SiC power module with 1nH commutation inductance," in Proc. 9th Int. Conf. Integr. Power Electron. Syst., 2016, pp. 1-6.
  10. [80]80. M. Horio, Y. Iizuka, and Y. Ikeda, "Packaging technologies for SiC power modules," Fuji Elect. Rev., vol. 58, no. 2, pp. 75-78, 2012.
  11. [118]118. W. Zhang et al., "A new package of high-voltage cascode gallium nitride device for megahertz operation," IEEE Trans. Power Electron., vol. 31, no. 2, pp. 1344-1353, Feb. 2016.
  12. [121]121. W. W. Sheng and R. P. Colino, "Materials," in Power Electronic Modules: Design and Manufacture, 1st ed. Boca Raton, FL, USA, CRC Press, 2004.

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Authors
Wang, L., Wang, W., Hueting, R. J. E., Rietveld, G., & Ferreira, J. A.
Affiliations
  • Guangdong Greater Bay Area Institute of Integrated Circuit and System (CN)
  • Yongjiang Laboratory (CN)
  • University of Twente (NL)
  • VSL National Metrology Institute (NL)
Venue
IEEE Transactions on Power Electronics
Published
2023-01
Volume
38
Issue
1
Pages
472-490
ISSN
  • 0885-8993 (ISSN-L)
  • 1941-0107
OpenAlex
W4292983478
Cited by
73
References
115
Citations by year
2026: 18 · 2025: 27 · 2024: 18 · 2023: 10
FWCI
3.77
Type
journal article
Language
en
Open access
Locations
  • IEEE Transactions on Power Electronics (publishedVersion)
  • University of Twente Research Information (acceptedVersion, other-oa)
  • University of Twente Research Information (submittedVersion, other-oa)
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Silicon Carbide Semiconductor Technologies
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Electronic Packaging and Soldering Technologies
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › 3D IC and TSV technologies
Keywords
wide bandgap semiconductors, power semiconductor packaging, silicon carbide, gallium nitride, aluminum wire bonding, parasitic inductance, interconnection materials, power modules, high-temperature power electronics

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