An implantable 700μW 64-channel neuromodulation IC for simultaneous recording and stimulation with rapid artifact recovery
Open accessAbstract
We present an 180nm HV CMOS IC for concurrent neural stimulation and recording that combines 64 low-noise recording front-ends and 4 independent stimulators multiplexed to any of the 64 channels. The stimulators have 5mA peak current, 12V compliance and dynamic power management to maximize efficiency. Co-design of the stimulation and recording subsystems resulted in 100mV of recording linear range, 70nV/rtHz noise, and a rapid 1ms (single-sample) artifact recovery during stimulation.
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A common solution is to prevent amplifier saturation via a wide linear input range.
“A common solution is to prevent amplifier saturation via a wide linear input range [194].”
From Active Neural Interface Circuits and Systems for Selective Control of Peripheral Nerves: A Review (2024) · cites this paper as [194]
Adaptive filtering methods rely on the least-mean-squares (LMS) algorithm to implement infinite impulse response (IIR) and finite impulse response (FIR) digital filters to address and cancel out individual samples of artifacts.
“Techniques such as adaptive filtering methods rely on the least-mean-squares (LMS) algorithm to implement infinite impulse response (IIR) and finite impulse response (FIR) digital filters to address and cancel out individual samples of artifacts [132], [194].”
From Active Neural Interface Circuits and Systems for Selective Control of Peripheral Nerves: A Review (2024) · cites this paper as [194]
The System Description and Measurements section describes rapid artifact recovery through the recording front-end’s linear range, reset switches, and stimulation charge balancing. Searches for LMS, adaptive filtering, FIR/IIR filters, and sample-by-sample artifact cancellation found no passage addressing the claimed method. No page numbers were provided in our copy. (LLM, conf=0.76)
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MethodOpamp-Less Sub-μW/Channel Δ-Modulated Neural-ADC With Super-GΩ Input Impedance
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“2 (middle) shows a state-of-the-art (SoA) architecture including an LNA and ADC combined in a single channel [3,4].”
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“However, the maximum input signal range is typically less than 400mV pp [16], which may not be suf fi cient given the large DEO combined with multiple sources of interference.”
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MethodSelf-citationNeuroBus - Architecture for an Ultra-Flexible Neural Interface
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“While existing systems [1-4] deliver electrical stimulation by placing electrodes in close proximity to target neurons, the capability for low-latency configurable stimulation that is spatially localized remains unrealized.”
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“Therefore, a fast-settling mechanism has been included in several designs [27], [28], [29] to minimize the effects of such artifacts.”
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“Recent implementations address these problems by migrating to highvoltage-compliant CMOS processes for stimulation [2,3] where large core devices are less suited for digital integration, overdesigning the recording front-end dynamic range to accommodate large stimulus artifacts [3], or using mixed-signal feedback in t…”
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“ing stimulation, a high voltage is usually applied to the CCS to accommodate a large voltage drop across ZETI, [61]–[63].”
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“A popular solution in recent years is the direct-digitization AFE (DD-AFE) [12], where a delta-sigma modulator ( ΔΣ M) is directly engaged to the electrodes, eliminating the need for an IA while providing a high dynamic range in a power-and area-efficient manner.”
Circuits and Architectures for Neural Recording Interfaces
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A Sub-mm$^3$ Ultrasonic Free-floating Implant for Multi-mote Neural RecordingPreprint
Ghanbari, M. M., Piech, D. K., Shen, K., et al. (2019) · arXiv (Cornell University) · doi:10.48550/arxiv.1905.09386 · Cited by 5 · see citing works
“When the signal is downmodulated, the kT/C noise is converted into out-of-band chopper ripple [23].”
BackgroundSelf-citationAn Artifact-Resilient Neural Recording Front-end with Rail-to-Rail DM and CM Offset Correction
Bandali, M., & Johnson, B. C. (2023) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas46773.2023.10182181 · Cited by 4 · see citing works
“While this is sufficient for most neural recording applications [19], [20], chopping the input at a higher frequency than the sampling rate to reduce flicker noise reduces the input impedance to Zin = 1/(4fchopCAC) [9], [21].”
BackgroundSelf-citationArtifact-Aware Analogue/Mixed-Signal Front-Ends for Neural Recording Applications
Pérez-Prieto, N., Delgado‐Restituto, M., & Rodriguez-Vazquez, A. (2019) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas.2019.8702656 · Cited by 4 · see citing works
“Another potential problem is the long recovery time after blanking unless proper techniques are adopted [9], [10].”
BackgroundMEDUSA: A Low-Cost, 16-Channel Neuromodulation Platform with Arbitrary Waveform Generation
Tala, F., & Johnson, B. C. (2020) · Electronics · doi:10.3390/electronics9050812 · Cited by 4 · see citing works
Self-citationAdaptive EMG-based hand gesture recognition using hyperdimensional computing.Preprint
Moin, A., Zhou, A., Benatti, S., et al. (2019) · arXiv (Cornell University) · Cited by 4 · see citing works
Self-citationA Wide-Dynamic-Range, DC-Coupled, Time-Based Neural-Recording IC With Optimized CCO Frequency
Youn, D., Kim, Y.-I., Choi, I., Jung, Y., Jeon, H., Lee, K., Kweon, S.-J., Ha, S., & Je, M. (2024) · IEEE Access · doi:10.1109/access.2024.3424228 · Cited by 3 · see citing works
“2(b)) [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28].”
On the ESD Protection for 10V-Compliant Neural Stimulator in 65nm CMOS Technology
Ahmad, N., Lashkare, S., & Somappa, L. (2025) · IEEE International Symposium on Circuits and Systems proceedings · doi:10.1109/iscas56072.2025.11044275 · Cited by 3 · see citing works
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“Linearization techniques for Gm-C integrator based ADCs include source degeneration, dynamic element matching [4] and capacitor coupled feedback architectures [7], [6].”
MethodSayed, G. M., Bartels, A., Dorigo, D. D., Fleiner, T., Roßkothen-Kuhl, N., & Kuhl, M. (2025) · IEEE Transactions on Biomedical Circuits and Systems · doi:10.1109/tbcas.2025.3563684 · Cited by 2 · see citing works
“In such scenarios, it is advantageous to increase the dynamic range of the recording frontend, to accommodate larger artifacts without saturation [9], [10].”
A Wearable Platform for Real-Time Control of a Prosthetic Hand by High-Density EMG
Molinari, R. G., Avilés-Carrillo, V., Villa, G. A. G. D., et al. (2026) · IEEE Access · doi:10.1109/access.2026.3670500 · Cited by 2 · see citing works
Technical Review: Neural Recording Circuits for Bidirectional Neural Interface
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“The design in [9] employs a similar topology based on the 1-”
Design of CMOS Circuits for Electrophysiology
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“…kT / C noise is usually not a big concern since it gets averaged and becomes negligible compared to the overall ADC input-referred noise due to the very infrequent reset operation [38], or converted into out-of-band chopper ripple and then filtered out by the subsequent integrator [45].”
Brain-inspired Multi-level Control of an Assistive Prosthetic Hand through EMG Task Recognition
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“The adapter PCB was re-designed to interface 5 force sensors and the flexible 64-channel sEMG electrode array with the WAND device [26] - an 8-layer PCB that accommodates an accelerometer, the custom-designed sensing and digitizing ASIC [27], and components for processing/telemetry.”
MethodSelf-citationA Neural Recording and Stimulation Chip with Artifact Suppression for Biomedical Devices
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“Reference [49] (REC and STIM) Reference [50] (REC and STIM) Reference [37] (REC and STIM) Reference [40] (REC and STIM) Reference [24] (REC and STIM) +is work (REC and STIM) Process 0.”
BackgroundFeasibility of Using the Utah Array for Long-Term Fully Implantable Neuroprosthesis Systems
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Design Considerations for Implantable Neural Circuits and Systems
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“Both DBS and FSCV generate stimulation artifacts as high as 100 mV at the interface of the neural recording analog front end (AFE), which can cause it to saturate [7], [8], [9], [10].”
A wireless, 60-channel, AI-enabled neurostimulation platform
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“Moreover, only [9] considers stimulator charge balance even though the link between residual charge in the electrodes (i.”
BackgroundAn Offset Charge Compensating Biphasic Neuro - stimulation for Faradaic DC-Current Reduction
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Biomimetic bidirectional hand neuroprostheses for restoring somatosensory and motor functions
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Restoring upper extremity function with brain-machine interfaces
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An Implantable 8-Contact Sense and Stimulation System for Continuous Recording
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“Prior work reported in the literature describing neuromodulation sense and stimulation module designs [6][10] have focused on different system considerations including designing for electrodes with significantly different impedances and designing for use in animal models where safety and reliability concerns are reduc…”
BackgroundAdvances in High-Resolution, Miniaturized Bioelectrical Neural Interface Design
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“The chopping technique mitigates flicker and kT/C noise using double integration with opposite polarities [12], [13], maintaining a small size for the input devices in the Gm-cell (NMOS: W/L = 8 × 2 .”
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“Recent improvements allow the amplifier to be connected immediately after stimulation [56], using mixed-signal circuit realization of the analog front-end (AFE).”
BackgroundEnergy-Efficient Electrical Stimulation Systems
Banerjee, A., & Nag, S. (2021) · Handbook of Neuroengineering · doi:10.1007/978-981-15-2848-4_104-2
Design Considerations for Implantable Neural Circuits and Systems
Hsu, W.-Y., Hsieh, P.-H., & Chen, H. (2021) · Handbook of Neuroengineering · doi:10.1007/978-981-15-2848-4_19-1
Advances in High-Resolution, Miniaturized Bioelectrical Neural Interface Design
Nguyen, A. T., Xu, J., Wu, T., Luu, D. K., & Yang, Z. (2021) · Handbook of Neuroengineering · doi:10.1007/978-981-15-2848-4_23-2
- Authors
- Johnson, B. C., Gambini, S., Izyumin, I., Moin, A., Zhou, A., Alexandrov, G., Santacruz, S. R., Rabaey, J. M., Carmena, J. M., & Muller, R.
- Affiliations
- University of California, Berkeley (US)
- ORCID
- Venue
- 2017 Symposium on VLSI Circuits
- Publisher
- IEEE
- Published
- 2017-06
- Pages
- C48-C49
- ISSN
- 2166-9600 (ISSN-L)
- OpenAlex
- W2742939082
- Cited by
- 119
- References
- 5
- Citations by year
- 2026: 8 · 2025: 13 · 2024: 10 · 2023: 10 · 2022: 12 · 2021: 16 · 2020: 15 · 2019: 16 · 2018: 18 · 2017: 1
- FWCI
- 27.15
- Type
- conference paper
- Language
- en
- Open access
- green
- escholarship.org
- Locations
- Symposium on VLSI Circuits (publishedVersion)
- eScholarship (California Digital Library) (submittedVersion)
- Topics
- Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
- Life Sciences › Neuroscience › Cellular and Molecular Neuroscience › Neuroscience and Neural Engineering
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
- Keywords
- neurostimulation, artifact recovery, low-power CMOS, HV-CMOS, dynamic power management
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