The DOI matches its Crossref record; 32 of the 33 references it cites were found in a registry or an index; none of the 95 sources its claims cite is checked for support yet.
Paralleling of IGBT Power Semiconductor Devices and Reliability Issues
Open accessAbstract
Paralleling of power semiconductor devices is inevitable considering their widespread application and exploitation in the extended horizon of these applications. However, paralleling of power semiconductor devices is prone to severe unbalancing corresponding to the non-idealities of device parameters, which leads to non-identical dynamic and static characteristics of the power devices, as well as the operating conditions and aging. Therefore, the currents are generally non-uniform and cause the derating of the system. This paper discusses and analyzes issues associated with the paralleling of IGBT power devices, which can evoke serious reliability issues. Furthermore, the paper examines the techniques and methodologies that have been proposed to reduce the issue of current unbalancing of parallel-connected power devices.
Overview
CoChat Summary
TL;DR
This review analyzes current imbalance and reliability issues when paralleling IGBT power devices, covering device, gate-driving, and layout parameters. It surveys passive and active gate-driving/current-balancing techniques, concluding that passive methods can reduce but not optimize sharing, while active methods improve balancing at higher complexity and cost.
Key findings
- Paralleling is necessary for high-current applications; a single Si-IGBT chip for 1200/1700 V is limited to approximately 200 A, motivating parallel chips, discrete devices, half-bridges/arms/legs, or modules.
- Current imbalance is categorized as static and dynamic. Static unbalancing is affected by on-state voltage/on-state resistance, gate-emitter voltage, junction temperature, and total loop resistance; dynamic unbalancing is affected by threshold voltage, gate signal propagation delay, rise/fall times, gate resistance, parasitic capacitances, power loop inductance, and gate loop inductance.
- Passive techniques—device matching, symmetric layout, common mode chokes, emitter feedback, and differential choke-based gate feedback—can improve or minimize imbalance but generally cannot realize optimized current sharing. Active gate control—gate delay control, gate voltage control, and dynamic gate resistance—can provide improved/optimized sharing but faces implementation complexity and cost.
- Reliability concerns include current imbalance up to 50% due to turn-off delay and turn-off voltage slope during turn-off, requiring turn-off current reduction by 50% to stay within SOA; thermal stability requires \((\partial P_G/\partial T) \le (\partial P_D/\partial T)\).
Methods
- Design: review and analysis of paralleling issues for IGBT power semiconductor devices, including device physics, system parameters, gate-driving topologies, and current-balancing techniques.
- Data/sample: no original experimental sample is reported; the paper synthesizes prior studies, manufacturer application notes, and referenced literature.
- Main analysis: categorizes static vs. dynamic current unbalancing, passive vs. active gate-driving/current-balancing methods, and summarizes system parameters and passive method performance in Table 1 and Table 2.
Limitations
- The paper states no explicit limitations section.
- Evident from the text: it is a review/synthesis without new experimental validation or original measurements.
- Evident from the text: some cited studies lack quantitative detail—for example, differences in unequal \(L_E\) and \(L_C\) are “not mentioned quantitatively” in reference [8].
Model-written summary. Check it against the paper before relying on it.
Integrity signals
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Cites
Statistics
Figures
![Figure 1 Current capability requirement corresponding to blocking voltage for application of power semiconductor devices [10]. Figure 1. Current capability requirement corresponding to blocking voltage for application of power semiconductor devices [10].](/paper-figures/4836b2945f7f4966a119e3d9f619b766/paralleling-of-igbt-power-semiconductor-devices-and-reliability-issues-figure-1.png)
![Figure 3 System components influencing the performance of parallel-connected power semiconductor devices [14,15,22,23]. Figure 3. System components influencing the performance of parallel-connected power semiconductor devices [14,15,22,23]. Figure 3. System components influencing the performance of parallel-connected power semiconductor devices [14,15,22,23].](/paper-figures/add1f672b9e74141bba35276f3518aea/paralleling-of-igbt-power-semiconductor-devices-and-reliability-issues-figure-3.png)
Verification
Claims the paper makes
42 Own interpretation · 41 No full text of the sources · 31 Not checked yet · 3 No basis given
In the paper
“One conventional approach to achieving the operating criterion considering thermal stability and the SOA limit is derating the chips/power modules [16].”
§ Paralleling of IGBT Power Semiconductor Devices and Reliability Issues > 3. Gate-Driving Techniques
What the sources say
- Not checked — no full text of the sourcecites [16] Schlapbach, U. (2010, January 16–18). Dynamic paralleling problems in IGBT module construction and application. Proceedings of the International Conference on Integrated Power Electronics Systems, Nuremberg, Germany.
plainstates a cause- Asserted: passes — The authors put it forward as true.
- Checkable: passes — It can be checked against evidence.
- Load-bearing: unclear — It is unclear whether the paper’s conclusions depend on it.
- Based: passes — The paper gives a reason why it holds.
A claim is checked only against the cited paper’s full text, never its abstract, and none is available for its sources.
In the paper
“Furthermore, applications of the medium voltage class, i.e., 3.3 kV, 4.5 kV, and 6.5 kV, for high-power industrial drives, have similar current limitation constraints [7][8][9].”
§ Paralleling of IGBT Power Semiconductor Devices and Reliability Issues > 1. Introduction
What the sources say
- Not checked — no full text of the sourcecites [7] Chen, 2014, Dynamic Characterization of Parallel-Connected High-Power IGBT Modules, IEEE Trans. Ind. Appl. source
- Not checked — no full text of the sourcecites [8] Werner, R., Weigel, J., Boehmer, J., and Eckel, H.-G. (2019, January 7–9). Potential of passive feedbacks to reduce dynamic current imbalances of paralleled IGBTs. Proceedings of the PCIM Europe International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nuremberg, Germany. source
- Not checked — no full text of the sourcecites [9] Jadhav, V., Zhou, Y., and Jansen, U. (2016, January 28–30). Analysis of different IGBT gate driver strategies influencing dynamic paralleling performance. Proceedings of the PCIM Asia International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Shanghai, China.
plain- Asserted: passes — The authors put it forward as true.
- Checkable: passes — It can be checked against evidence.
- Load-bearing: unclear — It is unclear whether the paper’s conclusions depend on it.
- Based: passes — The paper gives a reason why it holds.
In the paper
“The gate-driving layout determines the gate current path, and an asymmetric gatedriving layout results in parallel-connected power devices due to the asymmetric gate current path [9].”
§ Paralleling of IGBT Power Semiconductor Devices and Reliability Issues > 2.2. Gate-Driving Parameters
What the sources say
- Not checked — no full text of the sourcecites [9] Jadhav, V., Zhou, Y., and Jansen, U. (2016, January 28–30). Analysis of different IGBT gate driver strategies influencing dynamic paralleling performance. Proceedings of the PCIM Asia International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Shanghai, China.
plainstates a cause- Asserted: passes — The authors put it forward as true.
- Checkable: passes — It can be checked against evidence.
- Load-bearing: unclear — It is unclear whether the paper’s conclusions depend on it.
- Based: passes — The paper gives a reason why it holds.
A statement the paper makes itself — it cites no source for it, so there is none to check. The quote shows it is in the paper.
In the paper
“Device matching: Ensuring close matching of device parameters, such as Rds,on and VG,th, helps promote current sharing among parallel devices.”
§ Paralleling of IGBT Power Semiconductor Devices and Reliability Issues > 1. Introduction
plainstates a cause- Asserted: passes — The authors put it forward as true.
- Checkable: passes — It can be checked against evidence.
- Load-bearing: passes — The paper’s conclusions depend on it.
- Based: passes — The paper gives a reason why it holds.
In the paper
“The emitter feedback provides improved dynamic current sharing with an asymmetric gate drive length, as well as an asymmetric busbar configuration.”
§ Paralleling of IGBT Power Semiconductor Devices and Reliability Issues > 3.2.2. Emitter Feedback
What the sources say
- Not checked — no full text of the sourcecites [9] Jadhav, V., Zhou, Y., and Jansen, U. (2016, January 28–30). Analysis of different IGBT gate driver strategies influencing dynamic paralleling performance. Proceedings of the PCIM Asia International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Shanghai, China.
plainstates a cause- Asserted: passes — The authors put it forward as true.
- Checkable: passes — It can be checked against evidence.
- Load-bearing: passes — The paper’s conclusions depend on it.
- Based: passes — The paper gives a reason why it holds.
48 more claims
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Self-check
Percentages, sums and reported differences re-computed from the paper’s own numbers.
Each contradiction between two passages listed here was confirmed by an independent check.
Rated minor: it would not touch a result — a value no result rests on, a p-value that stays on the same side of the significance level, or a conflict that is clerical, resolved elsewhere in the paper, or outside its own findings.
In the paper
§ Paralleling of IGBT Power Semiconductor Devices and Reliability Issues > 3.3. Active Gate-Driving Control Techniques
“The active gate control methods are summarized in Figure 8 using a schematic representation of the techniques.”
§ Paralleling of IGBT Power Semiconductor Devices and Reliability Issues > 4.3. Reliability, Derating, and Stability Factors
“Figure 8. Schematic diagram of passive gate-driving technique for parallel-connected power devices: (a) common mode chokes; (b) emitter feedback through common auxiliary emitter; and (c) gate current feedback using differential mode chokes.”
Rated minor: it would not touch a result — a value no result rests on, a p-value that stays on the same side of the significance level, or a conflict that is clerical, resolved elsewhere in the paper, or outside its own findings.
In the paper
§ Paralleling of IGBT Power Semiconductor Devices and Reliability Issues > 1. Introduction
“The static and dynamic behavior of paralleled IGBTs was discussed in [17] in 1990.”
§ Paralleling of IGBT Power Semiconductor Devices and Reliability Issues > References
“17. Letor, R. Static and dynamic behaviour of paralleled IGBTs. IEEE Trans. Ind. Appl. 1992, 28, 359-402.”
Rated minor: it would not touch a result — a value no result rests on, a p-value that stays on the same side of the significance level, or a conflict that is clerical, resolved elsewhere in the paper, or outside its own findings.
In the paper
§ Paralleling of IGBT Power Semiconductor Devices and Reliability Issues > 4.1. Influence of Parameters and Passive Gate Control
“turn-off energy (∆E off ) with the collector-emitter voltage (∆V CE,sat ) and turn-off delay time (∆t dvoff )”
§ Paralleling of IGBT Power Semiconductor Devices and Reliability Issues > 4.1. Influence of Parameters and Passive Gate Control
“∆E on = f ∆V CE , ∆t dvo f f”
Citations
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Metadata
- Authors
- Tripathi, R. N., & Omura, I.
- Affiliations
- Kyushu Institute of Technology (JP)
- Corresponding author
- Tripathi, Ravi Nath
- ORCID
- Tripathi, Ravi Nath
- Venue
- Electronics
- Publisher
- MDPI AG
- Published
- 2023-09-10
- Volume
- 12
- Issue
- 18
- Pages
- 3826
- ISSN
- 2079-9292 (ISSN-L)
- OpenAlex
- W4386601598
- Semantic Scholar
- 3488f2ff2d684ac119add22dc7ede46b64e4abfb
- Cited by
- 14
- References
- 33
- Citations by year
- 2026: 5 · 2025: 5 · 2024: 3 · 2023: 1
- FWCI
- 1.00
- Type
- journal article
- Language
- en
- Open access
- gold
- doi.org
- Licence
- Locations
- Electronics (publishedVersion, cc-by)
- Institutional Repositories DataBase (IRDB) (publishedVersion, cc-by)
- Funders
- Japan Society for the Promotion of Science (JSPS) KAKENHI (20K14720.N)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Silicon Carbide Semiconductor Technologies
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Multilevel Inverters and Converters
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Electric Power Systems and Control
- Keywords
- IGBT, power semiconductor devices, reliability, current sharing, aging materials, derating
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