Cited by 132Analog and Mixed-Signal Circuit DesignNeuroscience and Neural EngineeringRadio Frequency Integrated Circuit Design

A 100-Channel 1-mW Implantable Neural Recording IC

Open access
Zou, Xiaodan, Liu, Lei, Cheong, Jia Hao, Yao, Lei, Li, Peng, Cheng, Ming-Yuan, Goh, Wang Ling, Rajkumar, Ramamoorthy +3 more·2013·IEEE Transactions on Circuits and Systems I: Regular Papers

Abstract

This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 μVrmsin a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-μm standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems.

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Crossref · 10.1109/tcsi.2013.2249175

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  • In some designs, when channels were not sampled by the ADC, they were put into a sleep mode in which power consumption was maintained at a level that minimized wake-up time.

    “For example, in [67, 156], when channels were not sampled by the ADC, they were put into a sleep mode where the channel’s power consumption was maintained at a level to minimize the wake-up time.”
  • Amplifiers using the current-reuse topology achieve state-of-the-art noise performance.

    “Amplifiers using this topology achieve state-of-the-art noise performance [49, 129, 156].”
  • Continued shrinking of fine-line CMOS processes has helped increase channel counts and add capabilities such as on-chip analog-to-digital conversion and digital radio transmission.

    “The steady reduction in fine-line CMOS technologies has contributed to increased channel counts [6, 77] and expanded capabilities, such as on-chip analog-to-digital conversion [49, 156] and digital radio transmission [16, 67].”
  • The inadequacy of NEF alone becomes more pronounced because recent works have reported operating supply voltages below 1 V.

    “This inadequacy becomes more pronounced, as recent works have reported operating supply voltages below 1 V [49, 129, 156].”
  • Recent works reported that careful design of the OTA A1 makes low current consumption and low input-referred noise easily achievable.

    “Recent works have also reported that by carefully designing the OTA A1, low current consumption and low input-referred noise are easily achievable [63, 141, 142, 156].”

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Cites

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Research works printed but not linked: 11

  1. M. Chae, W. Liu, Z. Yang, T. Chen, J. Kim, M. Sivaprakasam, and M. Yuce, "A 128-Channel 6 mW Wireless Neural Recording IC with on- the-Fly Spike Sorting and UWB Transmitter", in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 146-147.
  2. H. Wu and Y. P. Xu, "A 1V 2.3µW Biomedical Signal Acquisition IC", in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2006, pp. 58-59.
  3. R. M. Walker, H. Gao, P. Nuyujukian, K. Makinwa, K. V. Shenoy, T. meng, and B. Murmann, "A 96-Channel Full Data Rate Direct Neural Interface in 0.13µm CMOS," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2011, pp. 144-145.
  4. X. Zou, W.-S. Liew, L. Yao, and Y. Lian, "A 1V 22µW 32-Channel Implantable EEG Recording IC," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2010. pp. 126-127.
  5. M. Hesener, T. Eichler, A. Hanneberg, D. Herbison, F. Kuttner, and H. Wenske, "A 14 b 40 MS/s redundant SAR ADC with 480 MHz clock in 0.13 μm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 248-600.
  6. S.-K. Lee, S.-J. Park, Y. Suh, H. J. Park, and J. Y. Sim, "A 1.3µW 0.6V 8.7-ENOB Successive Approximation ADC in a 0.18µm CMOS," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2009, pp. 242-243.
  7. R. Muller, S. Gambini, and J. M. Rabaey, "A 0.013mm 2 5µW DC- Coupled Neural Signal Acquistion IC with 0.5V supply," in IEEE Int.
  8. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2011, pp. 302-303.
  9. R. Muller, S. Gambini, and J. M. Rabaey, "A 0.013mm 2 , 5 μW, DC- Coupled Neural Signal Acquisition IC With 0.5 V Supply," IEEE Journal of Solid-State Circuits, vol. 47, no.1, pp. 232-243, Jan. 2012.
  10. R. M. Walker, H. Gao, P. Nuyujukian, K. Makinwa, K. V. Shenoy, T. Meng, and B. Murmann, "A 96-Channel Full Data Rate Direct Neural Interface in 0.13µm CMOS," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2011, pp. 144-145.
  11. Jia Hao Cheong (M'12) received the B.Eng. and Ph.D. degrees in electrical and electronic engineering from Nanyang Technological University (NTU), Singapore, in 2005 and 2009 respectively. Since 2009 he has been with Institute of Microelectronics (IME), Agency for Science, Technology and Research (A*STAR), Singapore as a Scientist in the Biomedical IC group. Since he joined IME, he has worked on the development of wireless implantable sensor ASIC for blood flow measurement and for neural signal recording, as well as ultrasound imaging front-end ASIC. His research interests include biomedical circuit and system, low-power analog & mixed-signal circuit and system and oversampled ultrasound beamforming. He was awarded the Best Student Paper Award in IEEE International Conference on Electron Devices and Solid-state Circuits (EDSSC) 2008.

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Authors
Zou, X., Liu, L., Cheong, J. H., Yao, L., Li, P., Cheng, M.-Y., Goh, W. L., Rajkumar, R., Dawe, G. S., Cheng, K.-W., & Je, M.
Affiliations
  • Agency for Science, Technology and Research (SG)
  • Nanyang Technological University (SG)
  • National University Health System (SG)
Venue
IEEE Transactions on Circuits and Systems I: Regular Papers
Published
2013-10
Volume
60
Issue
10
Pages
2584-2596
ISSN
  • 1549-8328 (ISSN-L)
  • 1558-0806
OpenAlex
W2095273620
Cited by
132
References
32
Citations by year
2026: 3 · 2025: 6 · 2024: 7 · 2023: 5 · 2022: 11 · 2021: 10 · 2020: 10 · 2019: 9 · 2018: 13 · 2017: 11 · 2016: 23 · 2015: 12 · 2014: 10 · 2013: 2
FWCI
8.64
Type
journal article
Language
en
Open access
Locations
  • IEEE Transactions on Circuits and Systems I Regular Papers (publishedVersion)
  • DR-NTU (Nanyang Technological University) (submittedVersion)
Funders
Agency for Science, Technology and Research
Topics
  • Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
  • Life Sciences › Neuroscience › Cellular and Molecular Neuroscience › Neuroscience and Neural Engineering
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Radio Frequency Integrated Circuit Design
Keywords
implantable neural recording, neural interfaces, neural amplifier, weak inversion, successive approximation register ADC, low-power analog front-end, neural spikes, local field potentials, power management, CMOS integrated circuit

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