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PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning
Abstract
Convolution neural networks (CNNs) are the heart of deep learning applications. Recent works PRIME [1] and ISAAC [2] demonstrated the promise of using resistive random access memory (ReRAM) to perform neural computations in memory. We found that training cannot be efficiently supported with the current schemes. First, they do not consider weight update and complex data dependency in training procedure. Second, ISAAC attempts to increase system throughput with a very deep pipeline. It is only beneficial when a large number of consecutive images can be fed into the architecture. In training, the notion of batch (e.g. 64) limits the number of images can be processed consecutively, because the images in the next batch need to be processed based on the updated weights. Third, the deep pipeline in ISAAC is vulnerable to pipeline bubbles and execution stall. In this paper, we present PipeLayer, a ReRAM-based PIM accelerator for CNNs that support both training and testing. We analyze data dependency and weight update in training algorithms and propose efficient pipeline to exploit inter-layer parallelism. To exploit intra-layer parallelism, we propose highly parallel design based on the notion of parallelism granularity and weight replication. With these design choices, PipeLayer enables the highly pipelined execution of both training and testing, without introducing the potential stalls in previous work. The experiment results show that, PipeLayer achieves the speedups of 42.45x compared with GPU platform on average. The average energy saving of PipeLayer compared with GPU implementation is 7.17x.
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“Alternatives to overcome this lim-itationhavebeenproposed,asforinstancethesimulatordevelopedby Song et al. 246 to evaluate their PipeLayer architecture, which considers highly parallel designs based on the notion of parallelism granularity and weight replication.”
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Metadata
- Authors
- Song, L., Qian, X., Li, H., & Chen, Y.
- Venue
- 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)
- Publisher
- IEEE
- Published
- 2017-02
- Pages
- 541-552
- ISSN
- 1530-0897 (ISSN-L)
- OpenAlex
- W2613989746
- Cited by
- 833
- References
- 64
- FWCI
- 113.24
- Type
- conference paper
- Language
- en
- Open access
- closed
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